As the power density of modern integrated circuits continues to increase with shrinking feature size, power and temperature management become increasingly important. Thermal profiling, along side analog simulation, is crucial to designing large and power-hungry circuits (see IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(8):1211-1220, October 2000, “A temperature aware simulation environment for reliable ULSI chip design”, Y. K. Cheng and S. M. Kang; and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17(8):668-681, August 1998, “ILLIADS-T: An electro-thermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips”, Y. K. Cheng, et al.) Static thermal profile information can be used to place circuits on a die to maximize temperature uniformity, thereby reducing the peak temperature (see IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(2):253-266, February 2000, “Cell-level placement for improving substrate thermal distribution” C. H. Tsai and S. M. Kang.) Likewise, dynamic temperature profiling can be used to direct operation, e.g. halting the system when the circuit is too hot, or switching to a lower power mode.
Circuits that overheat beyond specified operating conditions may suffer timing failures, or become damaged for various reasons, including thermal runaway. Traditional power management in synchronous systems often involves transitions to different system states or modes, typically involving changes in clock frequencies or voltage levels. However, as computational operations are performed more rapidly and involve increasingly larger amounts of computational circuitry, it is becoming progressively harder to synchronize computational operations with reference to a single global clock signal. In many cases, enforcing such synchronization greatly constrains the performance of the computational circuitry. To remedy this problem, some designers have begun to investigate the possibility of using “asynchronous” circuits that do not operate with reference to a global clock signal, and are hence not constrained by the need to continually synchronize computational operations with the global clock signal. In many cases, such asynchronous circuits can increase computational speed by an order of magnitude or more.
Asynchronous circuits operate without any global clock, and use handshakes to move and communicate data. The data-driven nature of asynchronous circuits allows a circuit to idle with no switching activity when there is no work to be done. Increasing the computational speed of an asynchronous circuit causes the circuit to switch more frequently, resulting in increased power consumption and consequently a significant amount of heat. Computing systems typically employ various components to dissipate this heat, such as heat sinks and cooling fans. However, as the computational speed of semiconductor chips continues to increase, and as these chips are packed more closely together to minimize propagation delay between the chips, it is becoming progressively harder to effectively dissipate this heat. This leads to excessive heat buildup, which can cause a computer system to fail, and in some cases can permanently damage circuitry within the computer system.
Asynchronous circuits are capable of operating correctly in the presence of continuous and dynamic changes in delays. Sources of delay variation may include temperature, supply voltage, manufacturing, noise, radiation and other transient phenomena. The frequency of an asynchronous pipeline is determined by the gate delays on the critical path rather than an external frequency source. As the circuit heats up, the gate delays increase and the frequency naturally drops, thereby reducing the circuit's dynamic power consumption and self-heat generation. However, the natural negative feedback retardation of this self-heating rate is too weak to halt the increase in temperature (see “An Energy-Complexity model for VLSI computations”, J. A. Tierno. PhD thesis, California Institute of Technology, 1995.)
It would, thus, be useful to provide a method and apparatus that automatically regulates the performance, power consumption and resultant generated heat of asynchronous circuits.
Some conventional voltage reference circuits requiring PVT (process, supply voltage, temperature) independence have used diode or bipolar junction transistor (BJT) bandgap reference circuits to generate temperature dependent signals used in voltage and/or current compensation. Circuits such as these typically require a supply voltage of at least 1.3 volts. As technology improves, and components become smaller, the supply voltages continues to drop. Some current processors operate with supply voltages of 1.4 volts, close to the limit at which diode or BJT bandgap circuits will become ineffective for use as supply voltages due to the silicon bandgap of 1.23 volts.
In light of the increasing use of non-power supply voltages in integrated circuit devices, there is an additional need for thermal management circuits and methods to impose negligible implementation overhead.